This invention relates generally to imaging devices, and more particularly, to imaging devices with shared column circuitry.
Image sensors are commonly used in electronic devices such as cellular telephones, cameras, and computers to capture images. In a typical arrangement, an electronic device with an image sensor is provided with an array of image sensor pixels arranged in pixel rows and columns. Column sensing circuitry is typically coupled to each pixel column for reading out image signals from the image pixels.
One type of conventional image sensor features a single analog-to-digital (ADC) circuit that is connected to each column line in an image pixel array. The column ADC circuit processes signals provided from image sensor pixels in a selected row one column at a time (i.e., the ADC circuit samples and converts signals provided on a first column before sampling and converting signals provided on a second column in the image pixel array). Performing serial readout in this way requires a significant amount of time, especially for high resolution image pixel arrays, as each image pixel in a row must wait for the image pixel in a previous column to be read out.
In an effort to enhance column readout performance, column parallel readout image sensors have been developed. A typical column parallel readout image sensor includes one ADC circuit per column, allowing each column in the image pixel array to be sampled and converted simultaneously. These ADC circuit blocks are a major contributor to physical column height in an image sensor, and are typically the deciding factor for die size. Having one ADC circuit per column can also result in a substantial amount of power consumption.
It would therefore be desirable to be able to provide imaging devices with a reduced number of ADCs while also maintaining the improved speed of column parallel readout architecture.